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INTEGRATED CIRCUITS
UCB1100 Advanced modem/audio analog front-end
Preliminary specification Supersedes data of 1996 Apr 09 Version 1.2 1998 May 08
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
Version 1.2
GENERAL DESCRIPTION
The UCB1100 is a single chip, integrated mixed signal audio and telecom codec. The single channel audio codec is designed for direct connection of a microphone and speaker. The built-in telecom codec can directly be connected to a DAA and supports high speed modem protocols. The incorporated 10 bit analogue to digital converter and the touch screen interface provides complete control and readout of a connected 4 wire resistive touch screen. The 10 additional general purpose I/O pins provides programmable inputs and/or outputs to the system. The UCB1100 has a serial interface bus (SIB) intended to communicate to the system controller. Both the codec input and output data and the control register data is multiplexed on this SIB interface.
UCB1100
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 KEY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.0 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . 3 2.0 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.0 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . 4 4.0 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . 5 5.0 PINOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5.1 PINLIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.0 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 8 6.1 AUDIO CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.1.1 AUDIO INPUT SPECIFICATIONS . . . . . . . . 10 6.1.2 AUDIO OUTPUT SPECIFICATIONS . . . . . . . 11 6.2 TELECOM CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2.1 TELECOM INPUT SPECIFICATIONS . . . . . 14 6.2.2 TELECOM OUTPUT SPECIFICATIONS . . . 15 6.3 TOUCH SCREEN MEASUREMENT MODES . . . . 16 6.3.1 POSITION MEASUREMENT . . . . . . . . . . . . . 16 6.3.2 PRESSURE MEASUREMENT . . . . . . . . . . . 16 6.3.3 PLATE RESISTANCE MEASUREMENT . . . 16 6.4 TOUCH SCREEN INTERFACE . . . . . . . . . . . . . . . . . 17 6.4.1 TOUCH SCREEN SPECIFICATIONS . . . . . 18 6.5 10 BIT ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5.1 SPECIFICATION OVERVIEW . . . . . . . . . . . . 21 6.6 ON CHIP REFERENCE CIRCUIT . . . . . . . . . . . . . . 21 6.6.1 SPECIFICATION OVERVIEW . . . . . . . . . . . . 21 6.7 SERIAL INTERFACE BUS . . . . . . . . . . . . . . . . . . . . . 22 6.7.1 SIB DATA FORMAT . . . . . . . . . . . . . . . . . . . . . 23 6.7.2 CODEC DATA TRANSFER . . . . . . . . . . . . . . 24 6.7.3 CONTROL REGISTER DATA TRANSFER . 26 6.7.4 AC ELECTRICAL CHARACTERISTICS . . . 27 6.8 GENERAL PURPOSE I/Os . . . . . . . . . . . . . . . . . . . . 27 6.9 INTERRUPT GENERATION . . . . . . . . . . . . . . . . . . . 27 6.10 RESET CIRCUITRY . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.0 MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 POWER ROUTING STRATEGY . . . . . . . . . . . . . . . . 29 8.0 CONTROL REGISTER OVERVIEW . . . . . . . . . . . . . . . . . . 30 9.0 PACKAGE OUTLINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1 PACKAGE OUTLINE LQFP48 . . . . . . . . . . . . . . . . . . 34 10.0 DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
APPLICATIONS
* Personal Intelligent Communicators * Personal Digital Assistants (PDA) * Screen phones * Smart Phone and smart Fax * Intelligent Communicators
KEY FEATURES
* 48-pin LQFP (SOT313-2) small body SMD package and low
external component count result in minimal PCB space requirement.
* A 12-bit sigma delta audio codec with programmable sample rate,
input and output voltage levels, capable of connecting directly to speaker and microphone, including digitally controlled mute, loopback and clip detection functions
* A 14-bit sigma delta telecom codec with programmable sample
rate, including digitally controlled input voltage level, mute, loopback and clip detection functions. The telecom codec is intended for direct connection to a DAA (digital access arrangement) and includes a built-in sidetone suppression circuit.
* A complete 4 wire resistive touch screen interface circuit
supporting position, pressure and plate resistance measurements.
* A 10-bit successive approximation ADC with internal track and
hold circuit and analogue multiplier for touch screen readout and monitoring of four external high voltage (7.5V) analogue voltages.
* A high speed, 4 wire serial interface data bus (SIB) for
communication to system controller.
* A 3.3V supply voltage and built in power saving modes make the
UCB1100 optimal for portable and battery powered applications.
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1998 May 08
Vssa1 Vdda1 2xVssd 2xVddd audio_input_enable loopback mux 64fs 1 bit ADC 1 encoder 12 digital decimation filter serial bus sibdout fs gain[0,2] 64fsa test
Philips Semiconductors
micp
gain[3,4]
micgnd
vdda2 64fs 4 bit DAC 4 serial bus controller attn[0,3] mute attn[4,5] audio_output_enable telecom input enable loopback attenuation mux 64fs 1 bit ADC 4 14 digital decimation filter fs effect 64fsa 12 digital volume control digital noise shaper fs
vssa1
AUDIO CODEC
spkrp spkrn
sibsync sibclk
1.0 FUNCTIONAL BLOCK DIAGRAM
control data registers
vssa2
to all other analog and digital blocks
side tone suppression echo on
serial bus sibdin decoder fsa 64fsa fst 64fst reset internal reset sample frequency divider stretcher nreset sample frequency divider
tinp tinn
TELECOM CODEC
64fs 4 bit DAC 4 mute telecom output enable divaud[0:6] touch screen bias voltage voltage reference power control divtel0:6] external reference external filter effect 14 digital noise shaper fs
Advanced modem/audio analog front-end
Figure 1. Block Diagram of the UCB1100
3
to external register 11 mux 10 bit ADC 9 to 1 track & hold 10 stop logic ADC start adc start sync enable adc_sync_ena adcsync
toutp toutn
vrefbyp
tsmx tspy tsmy vssa3
touch screen
Interrupt controller
irqout
switch matrix
eanble data interrupt data for all from other blocks analog blocks clear_interrupt[0:15] rising_edge_ena[0:15] falling_edge_ena[0:15] IOmode[0:9] IOwdat[0:9] IOrdat[0:9]
ad0 ad1 ad2 ad3
switched voltage dividers
Programmable IO pin block
io0 io1 io2 io3 io4 io5 io6 io7 io8 io9
digital pin
analog pin
Preliminary specification
UCB1100
SN00126
supply pin
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
AAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAA A A A A AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAA AAAAAAAAAAA
DESCRIPTION ORDERING CODE PACKAGE DRAWING SOT313-2 Plastic low profile quad flat package; 48 leads UCB1100LP/X3
2.0 ORDERING INFORMATION
3.0 ABSOLUTE MAXIMUM RATINGS
SYMBOL VDDMAX VIMAX VADMAX VOMAX IIKMAX IOKMAX IOLMAX Tstg Supply voltage
PARAMETER
MIN -0.5 -0.5 -0.5 -0.5
MAX 5.0 VDD+0.5 8.5 VDD+0.5 10 10 4
UNIT V V V V mA mA mA C
DC input voltage, except AD0-3 inputs DC input voltage AD0-3 inputs DC output voltage DC diode input current, all inputs DC diode output current Continuous output current, digital outputs Storage temperature
-55
150
NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the Absolute Maximum Rating section of this specification is not implied. 2. This product includes circuitry specially designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid submitting the UCB1100 to conditions exceeding the maximum ratings. 3. Parameters are valid over the operating ambient temperature unless otherwise specified. All voltages are with respect to the VSSD pin, unless otherwise noted.
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
4.0 DC ELECTRICAL CHARACTERISTICS
Tamb = 0C to 70C, VSSD = VSSA1 = VSSA2 = VSSA3 = 0V, sibclk = 10MHz, audio_divisor = 12, telecom_divisor = 40. Voltage with respect to the VSSD pin, unless otherwise specified. LIMITS SYMBOL VDDD VDDA1 VDDA2 VSSA2 VSSA3 IDDD PARAMETER digital supply voltage analogue supply voltage (excl.speaker driver) analogue supply voltage (speaker driver only) analogue ground voltage wrt. VSSD analogue ground voltage wrt VSSD digital supply current, full functionality only audio codec activated only telecom codec activated only touch screen activated only adc activated no functions activated, sibclk stopped analogue supply current, full functionality only audio codec activated only telecom codec activated only touch screen activated only adc activated no analogue functions activated total speaker driver supply current full functionality only audio codec activated only telecom codec activated only touch screen activated only adc activated no analogue functions activated touch screen bias voltage maximum touch screen bias current full scale voltage ad0-ad3 inputs full scale input touch screen inputs input low voltage input high voltage output low voltage output high voltage clock frequency Operating Ambient Temperature IOL=2mA IOH=2mA 0.8*VDDD 0 0 10 15 70 -0.5 0.7*VDDD 10 7.5 7.5 0.3*VDDD VDDD+0.5 0.2*VDDD Note 1 19 17 19 15 15 10 Note 1, Note 2 3.8 1.5 1.7 0.4 0.5 <10 Note 1, Note 2 0.2 0.2 10 10 10 10 1.8 mA mA A A A A V mA V V V V V V MHz C mA mA mA mA mA A mA mA mA mA mA A NOTES MIN 3.0 3.0 3.0 -0.4 -0.4 TYP 3.3 3.3 3.3 0 0 MAX 3.6 3.6 3.6 0.4 0.4 V V V V V UNIT
IDDA1
IDDA2
VTSCB ITSCB VADFS VTSFS VIL VIH VOL VOH fSIBCLK Tamb
NOTES: 1. Indicative value only. Value will be frozen following silicon measurements. 2. Excluding connected touch screen and speaker load currents.
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
5.0 PINOUT
44 not used 39 sibsync 40 sibdout 38 nreset 42 sibdin 43 irqout 41 sibclk 48 vddd 37 vssd 36 io3 35 io2 34 io1 33 io0 32 vddd 31 not used 30 tspx 29 tsmy 28 tsmx 27 tspy 26 vssa3 25 ad0 test 13 tinn 14 tinp 15 vrefbyp 16 vdda1 17 vssa1 18 not used 19 micgnd 20 micp 21 ad3 22 ad2 23 ad1 24 47 io6 46 io5 45 io4
io7 io8 io9 adcsync vssd not used vssa2 spkrn sprkp
1 2 3 4 5 6 7 8 9
UCB1100 LQFP48
TOP VIEW
vdda2 10 toutp 11 toutn 12
SN00127
Figure 2. LQFP48 (SOT313-2)
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
5.1 Pinlist
PINNING SYMBOL LQFP48 vddd vssd vdda1 vssa1 vdda2 vssa2 vssa3 sibclk sibdin sibdout sibsync irqout micp micgnd sprkp spkrn tinp tinn toutp toutn ad0-3 tspx tsmx tspy tsmy adcsync vrefbyp io0-9 32, 48 5, 37 17 18 10 7 26 41 42 40 39 43 21 20 9 8 15 14 11 12 25-22 30 28 27 29 4 16 33-36, 45-47, 1-3 38 13 6, 19, 31, 44 supply ground supply ground supply ground ground CMOS input CMOS input CMOS output CMOS input CMOS output active-High analogue input analogue input analogue output analogue output analogue input analogue input analogue output analogue output analogue input analogue IO analogue IO analogue IO analogue IO digital input analogue IO CMOS IO Hi-Z input `0' Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z `0' / Hi-Z PIN TYPE RESET STATE digital supply digital ground analogue supply analogue ground analogue speaker driver supply analogue speaker driver ground touch screen switch matrix ground SIB serial interface master clock SIB data input SIB data output SIB synchronization interrupt output microphone signal input microphone ground switch input positive speaker output negative speaker output positive telecom codec input negative telecom codec input positive telecom codec output negative telecom codec output analogue high voltage inputs positive X-plate touch screen negative X-plate touch screen positive Y-plate touch screen negative Y-plate touch screen adc synchronization pulse input external reference voltage input, external filter connection general purpose IO pins 3 3 3 3 3 3 2 1 1 DESCRIPTION NOTE
nreset test not used
CMOS input active-Low CMOS input `0'
asynchronous reset input test mode protection not connected pins 4
NOTES: 1. The vssd and vssa1 pins are connected to each other within the UCB1100. 2. The first 64 bits of the sib frame will be `0', the remaining bits in the sib frame will be Hi-Z. 3. The spkrp/spkrn, tinp/tiln and toup/toutn are differential pairs. 4. The test pin contains a internal pull down. This pin should be connected to vssd in normal mode of the UCB1100.
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.0 FUNCTIONAL DESCRIPTION
The UCB1100 consists of several analogue and digital sub circuits which can be programmed via the Serial Interface Bus (SIB). This enables the user to set the UCB1100 functionality according actual application requirements.
For example, a serial clock of 10 MHz, with a divisor of 14, results in an audio sample rate of 22.321kHz. Both the rising and the falling edges of the sibclk are used in case an odd audio_divisor is set. Thus a 50% duty cycle of the sibclk signal is mandatory to obtain time equidistant sampling with odd divisors. The frequency response of the audio codec depends mainly on the selected sample rate, since the bandwidth is limited in the down and up sampling filters. These digital filters both contain several FIR and IIR low pass filters and a DC removal filter (high pass filter). A 1st order analogue anti aliasing filter is implemented at the input of the microphone input to prevent aliasing in the adc path. A 3rd order smoothing filter is implemented between dac and speaker driver stage to reduce the spurious frequencies at the speaker outputs. The audio codec input (=ADC) and output (= DAC) paths can be enabled individually by setting the audio_adc and/or audio_dac bits in the audio control register B. These enable bits operate both on the associated analogue and digital functions, for optimal power control of both the analogue and the digital parts.
6.1 Audio codec
The audio codec contains an input channel, built up from a 64 times oversampling sigma delta analogue to digital converter (ADC) with digital decimation filters and a programmable gain microphone preamp. The output path consists of a digital up sample filter, a 64 time oversampling 4 bit digital to analogue converter (DAC) circuit followed by a speaker driver, capable of driving directly a low impedance bridge tied (BTL) speaker. The output path features digitally programmable attenuation and a mute function. The audio codec also incorporates a loopback mode, in which codec output path and the input path are connected in series. The audio sample rate is derived from the SIB interface clock pin (SIBclk) and is programmable through the SIB interface. The audio sample rate is given by the following equation:
Fsa +
(2 * Fsibclk) (64 * audio_divisor)
(5 t audio_divisor t 128)
audio_input_enable micp gain[3,4] loopback mux micgnd loop input vssa1 1 bit ADC 1 gain[0,2] 64fsa 64fs
fs +3dB 16 Sinc4 FIR low pass FIR half band FIR round up 4 2 2 2 DC removal half band WDF half band WDF +3dB 2 2 half band WDF DC removal fs 12 2 round up 12
interpolator
vdda2 spkrp spkrn vssa2 mute
loop input 64fs 4 bit DAC 4 attn[0,3] 64fsa digital volume control
noise shaper
attn[4,5] audio_output_enable
SN00128
Figure 3. Detailed Block Diagram Audio codec
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
UCB1100 vdda1 micp vdda1 micp
UCB1100
micgnd vssa1
micgnd vssa1
The output level can be attenuated in 3dB steps down to -69dB. The 8 highest attenuation steps are implemented in the analogue circuitry, while the two 24dB steps are implemented in the digital domain. This preserves the `audio quality' of the output signal at lowest attenuation settings. The speaker driver is muted when the audio-mute bit in the audio control register B is set. The speaker driver will remain activated in that case, however no signal is produced by the speaker driver circuitry.
UCB1100
UCB1100
UCB1100
`Passive' Microphone
`Active' Microphone
SN00129
spkrp spkrp spkrp
Figure 4. Possible Microphone Connections
spkrn spkrn spkrn
The UCB1100 audio codec input path accepts microphone signals directly, only a DC blocking capacitor is needed, since the micp input is biased around 1.4V. The `ground' side of the microphone is either connected to the analogue ground (vssa1) or to the micgnd pin of the UCB1100. The latter will decrease the current consumption of active microphones, since the micgnd pin is made Hi-Z when the audio codec input path is disabled. The full scale input voltage of the audio input path is programmable in 1.5dB steps by setting the appropriate data in the audio-input-gain bits in the audio control register A. A clip detection circuit will inform the user whenever the input voltage exceeds the maximum input voltage. In that case the clip detect status bit in audio control register B is set. An interrupt is generated on the irqout pin of the UCB1100 whenever the enable audio clip detect rising interrupt or the enable audio detect falling edge interrupt bit is set in the rising edge interrupt enable or falling edge interrupt control register B is set.
Bridge Tied Speaker Load
Single Ended Speaker Connections
SN00131
Figure 6. Possible Speaker Connections The speaker driver is designed to directly drive a bridge tied load (BTL). This yields the highest output power and it does not require external DC blocking capacitors. The speaker driver also accepts single ended connection of a speaker, in which case the maximum output power is reduced to a quarter of the BTL situation. Consequently this way of connecting the speaker to the speaker driver reduces the power consumption of the speaker driver in the UCB1100 by a factor of 2. Figure 6 shows possible ways to connect a speaker to the UCB1100. The audio input and output path are activated independently; the input path is enabled when the audio-input-enable bit is set, the output path is enabled when the audio-output-enable bit is set in the audio control register B. This provides the user the means to reduce the current consumption of the UCB1100 if one part of the audio codec is not used in the application. The audio codec has a loopback mode for system test purposes, which is activated when the audio_loopback enable bit in the audio control register B is set. This is an analogue loopback which internally connects the output of the audio output path to the input of the audio input path, (see Figure 3). In this mode the normal microphone input is ignored, but the speaker driver can be operated normally.
48dB digital attenuation analog attenuation
24dB
0dB
21dB
0dB 24dB 48dB 69dB
programmed attenuation
SN00130
Figure 5. Analogue and Digital Attenuation Settings Audio Output Path
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.1.1 Audio Input Specifications
LIMITS SYMBOL FSA VINAM VMICP RINPAI RHINE GSA NAGS GmA GEAR ROESAI DNAAI THUDAI THDMGAI SNRAI SNRMGAI RIPIA SBRIA EIA PARAMETER audio sample frequency full scale input voltage DC bias voltage micp input input impedance impedance micgnd to vssa1 gain step size number of gain steps maximum gain gain error (accuracy of gain setting) resolution audio input differential non linearity audio input ADC total harmonic distortion total harmonic distortion signal to noise ratio audio input signal to noise ratio pass band ripple stop band rejection audio input out of band rejection audio input 0db input gain selected 0.28Vpp, 1kHz to micp 46.5dB gain setting, 1mVpp, 1kHz to micp 0dB input gain selected 0.28Vpp, 1kHz to micp 46.5dB gain selected 1mVpp, 1kHz to micp FPLAI 20kHz 70 t.b.f. 65 50 0.5 0 dB gain setting, full scale input voltage -1 0 dB gain setting audio input path enabled audio input path enabled audio input path enabled 1.3 1.5 32 46.5 0 12 0.9 0.03 0.1 1 dB dB bit LSB % % dB dB dB dB mVrms 0.28 1.4 25 100 1.7 CONDITIONS MIN TYP MAX 26 kHz Vpp V k dB UNIT
NOTE: Coding scheme for ADC output data is 2's complement.
RIPIA 0dB
SBRIA FPLA FREQUENCY (Hz) FPHA FSHA
SN00132
Figure 7. Audio Input Path Frequency Response
1998 May 08
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FPLA = 0.00016 * FSA FPHA = 0.42 * FSA FSHA = 0.6 * FSA
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.1.2 Audio Output Specifications
LIMITS SYMBOL VOFFIA VOOA VOFFOA VSPK ASOA NSOA AMOA ROESOA DNAOA THUDOAS THUDOAH SNROAS SNROAH RIPOA FSUOA SBROA EIOA ZSPKR offset error full scale output voltage offset error DC bias voltage spkrp and spkrn pin attenuation step size number of attenuation steps maximum attenuation resolution differential non linearity DAC total harmonic distortion 16 speaker total harmonic distortion 1k headphone signal to noise ratio 16 speaker signal to noise ratio, 1kH headphone pass band ripple cut off frequency upper stop band stop band rejection integrated out of band energy speaker impedance FSHAO 20kHz 8 70 30 16 0dB attenuation 20Hz to 20kHz 0dB attenuation 20Hz to 20kHz bandwidth 0dB attenuation 20Hz to 20kHz bandwidth 0dB attenuation 20Hz to 20kHz bandwidth FPLAO < Fsig <- FPHAO 40 65 80 80 0.5 0.6 0.5 PARAMETER CONDITIONS MIN No signal applied to micp 0dB attenuation, 16ohm speaker differential Spkrp-Spkrn 16ohm speaker Audio output path enabled 2.8 1.4 3.0 24 69 12 0.9 2 0.03 dB bit LSB % % dB dB dB FSA dB mVrms 3.2 TYP 0 3.2 50 MAX LSB Vpp mVpp V dB UNIT
NOTE: Coding scheme for DAC input data is 2's complement.
RIPOA 0dB
SBROA FPLA FREQUENCY (Hz) FPHA FSHA
SN00133
Figure 8. Audio Output Filter Frequency Response
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FPLA = 0.00016 * FSA FPHA = 0.42 * FSA FSHA = 0.6 * FSA
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.2 Telecom codec
The telecom codec contains an input channel, built up from a 64 times oversampling sigma delta analogue to digital converter (ADC) with digital decimation filters, programmable attenuation and build in sidetone suppression circuit. The output path consist of a digital up sample filter, a 64 time oversampling 4 bit digital to analogue converter (DAC) circuit followed by a differential output driver, capable of directly driving a 600ohm isolation transformer. The output path includes a mute function. The telecom codec also incorporates a loopback mode, in which codec output path and the input path are connected in series. The telecom sample rate is derived from the SIB interface clock pin (sibclk) and is programmable through the SIB interface. The telecom sample rate is given by the following formula:
edges of the sibclk are used in case an odd telecom_divisor is set. In that case a 50% duty cycle of the sibclk signal is mandatory to obtain time equidistant sampling. The input path of the telecom codec has a programmable attenuation. It also implements a voice band filter, which consists of an digital low pass filter, which is a part of the decimation filter. Therefore the pass band of the voice band filter is determined by the selected telecom codec sample rate. This voice band filter is activated by the high pass enable bit in the telecom control register B. The resulting telecom input filter curves are given in Figures 11 and 12. The output section of the telecom codec is designed to interface with a 600 ohm line through an isolation transformer. The built in mute function is activated by the mute bit in the telecom control register B. The output driver remains active in the mute mode, however no output signal is produced.
Fst +
(2 * Fsibclk) (64 * telecom_divisor)
(5 t telecom_divisor t 128)
For example, a sibclk of 10 MHz, with a divisor of 40, results in a telecom sample rate of 7.813kHz. Both the rising and the falling
side tone suppression echo on tinp tinn
telecom input enable loopback attenuation mux 1 bit ADC 4 64fs effect
loop inputs
fs +3dB 16 Sinc4 FIR DC removal half band WDF 2 half band WDF 2 high pass FIR half band FIR +3dB 2 2 DC removal fs round up 2 2 14 round up 14
low pass FIR
half band FIR
half band FIR
loop inputs noise shaper toutp toutn 64fs 4 bit DAC 4 mute effect telecom output enable 4
interpolator
SN00134
Figure 9. Detailed Block Diagram Telecom codec
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
toutp Ro 1:1 transformer A Rt Rt tinp Ri Rs Rg
An important built in feature of the telecom codec is the sidetone suppression circuit. The sidetone suppression circuit is activated when the sidetone suppression enable bit in the telecom control register B is set. The telecom input signal contains a large part of the telecom output signal Tout, when the sidetone suppression circuit is disabled. The available dynamic range of the telecom input is occupied largely by the telecom output voltage. The sidetone suppression circuit subtracts a part of the telecom output signal from the telecom input signal when activated. The available dynamic range is in that case used more effectively than without sidetone suppression.
Rt B
Rt tinn
Rs Ri Ro toutn Rg
The built in side tone suppression circuit, shown in Figure 9, has a fixed subtraction ratio, set be the resistors Rs and Ri, which equals 600 / 456. This ratio is calculated from the following relations: The impedance seen by the telephone line equals:
Rline + 2 * Rt ) Rt ) Ro * Ri Ro ) Ri
SN00135
Figure 10. Telecom codec Sidetone Suppression Circuitry Shown with the Typical Connection between UCB1100 and Telephone Line (No Protections Circuits Shown)
In which Rt represents winding resistance of the transformer, divided by 2. Assuming Ri >> Ro then
Rline + Rt ) Rt ) Ro + 600 + 300 2
A typical transformer has 156 ohm winding impedance, thus Re should be 144 ohm. The ratio of the telecom input and output voltage is therefore
Tin + Tout *
156 ) 300 + Tout * 456 156 ) 300 ) 144 600
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.2.1 Telecom Input Specifications
LIMITS SYMBOL FST VINTM VTIN ASIT NSTI AMTI AERTI RTI SINADTI SINADTIS DNLTI RESTI RIPTI RIPVTI SBRVTI SBRHTI SSUP PARAMETER sample frequency full scale input voltage DC bias voltage Tinp / Tinn pins attenuation step size number of attenuation steps maximum attenuation attenuation error (accuracy of attenuation setting) input impedance total harmonic distortion + noise to signal ratio total harmonic distortion + noise to signal ratio differential non linearity ADC resolution pass band ripple, no voice filter pass band ripple, voice filter activated stop band rejection, voice filter activated stop band rejection sidetone suppression effectiveness FPLTI < Fsig < FPHTI FVHTI < Fsig < FPHTI Fsig < FVLTI FSHTI NOTE: Coding scheme for ADC output data is 2's complement.
RIPTI 0dB 0dB
RIPTI
SIBVTI
SBRHTI FPLT FREQUENCY (Hz) FPHT FSHT
SIBHTI FVLT FVHT FREQUENCY (Hz) FPHT FSHT
SN00136
SN00137
Figure 11. Telecom Input Frequency Response, No Voice Filter
Figure 12. Telecom Input Frequency Response, Voice Filter Enabled
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FPLT = 0.00016 * FST FPHT = 0.42 * FST FSHT = 0.6 * FST FVLT = 0.018 * FST FVHT = 0.05 * FST 1998 May 08 14
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.2.2 Telecom Output Specifications
LIMITS SYMBOL FST VOOT VTOUT ROESTO SINADTO RIPTO RIPVTO SBRVTO SBRTO EITO ZTELTO VOFFTO PARAMETER sample frequency full scale output voltage DC bias voltage Toutp / Toutn pins resolution signal to noise + distortion pass band ripple pass band ripple, voice band filter activated stop band rejection, voice filter activated stop band rejection integrated out of band energy minimal load impedance offset error (deviation of the analogue output from zero with 0 code input to telecom output path) Fsig < FVLT FSHT < Fsig Frequencies > FST 600 70 25 dB mVrms 50 mV differential Toutp/Toutn telecom output path enabled 4.0 1.4 14 75 0.6 0.6 CONDITIONS MIN TYP MAX 10 4.4 UNIT kHz Vpp V bit dB dB dB
1200 load
NOTE: Coding scheme for the DAC input data is 2's complement.
RIPTO 0dB
SBRHTO FPLT FREQUENCY (Hz) FPHT FSHT
SN00138
Figure 13. Telecom Output Frequency Response, No Voice Filter
1998 May 08
15
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
FPLT = 0.00016 * FST FPHT = 0.42 * FST FSHT = 0.6 * FST
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.3 Touch Screen Measurement Modes
The UCB1100 contains an on chip interface for a 4 wire resistive touch screen. This interface supports three modes of touch screen measurements, position, pressure and plate resistance.
6.3.3 Plate Resistance Measurement
The plate resistance of a touch screen varies typically a lot due to processing spreads. Knowing the actual plate resistance makes it possible to compensate for the plate resistance effects in the pressure resistance measurements. Secondly the plate resistance decreases when two or more spots on the touch screen are pressed. In that case a part of one plate, e.g. the X plate is shorted by the other plate, which decreases the actual plate resistance. The plate resistance measurement is executed in the same way as the pressure resistance measurement. In this case only one of the two plates is biased and the other plate is kept floating. The current through the connected plate is again a direct indication of the connected resistance.
6.3.1 Position Measurement
Two position measurements are needed to determine the location of the pressed spot. First an X measurement, secondly a Y measurement. The X plate is biased during the X position measurement the X plate and the voltage on one or both Y terminals (tspy, tsmy) measured. The circuit can been represented by a potentiometer, with the tspy and/or tsmy electrode being the `wiper'. The measured voltage on the tspy/tsmy terminal is proportional to the X position of the pressed spot of the touch screen. In the Y position mode the X plate and Y plate terminals are interchanged, thus the Y plate is biased on the voltage on the tspx and/or tsmx terminal is measured.
Vtscbias
iplate
tspx Vposition Vtscbias tsmy tspx
Xplate
tsmy
tsmx
tspy
Figure 16. Touch Screen Setup for Plate Resistance Measurement
SN00139
Figure 14. Touch Screen Setup for Position Measurement
6.3.2 Pressure Measurement
The pressure used to press the touch screen can be determined. In fact the contact resistance between the X and Y plate is measured, which is a good indication of the size of the pressed spot and the applied pressure. A soft stylus, e.g. a finger, leads to a rather large contact area between the two plates when a large pressure is applied. A hard stylus, e.g. a pen, leads to less variation in measured contact resistance since the contact area is rather small. One plate is biased at one or both terminals during this pressure measurement, whereas the other plate is grounded, again on one or both terminals. The current flowing through the touch screen is a direct indication for the resistance between both plates. A compensation for the series resistance, formed by the touch screen plates itself will improve the accuracy of this measurement.
Vtscbias ipresure
Figure 15. Touch Screen Setup for Pressure Measurement
1998 May 08
IIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIII
tspx
Xplate
tsmy
tsmx
tspy
SN00140
16
IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII
Xplate tsmx tspy
IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII
SN00141
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.4 Touch Screen Interface
The UCB1100 contains a universal resistive touch screen interface for 4 wire resistive touch screen, capable of performing both position, pressure and plate resistance measurements. In addition the touch screen can be programmed to generate interrupts when the touch screen is pressed. The last mode is also active when the UCB1100 is set in the standby mode.
Vdda Rint
comparator
tsmy
tspx
tsmx
tspy
tsmy
tsc_mod_sel
vdda1
ts.. power
touch screen bias voltage
ts.. ground
vssa3 vssa1 touch screen current monitor
Figure 18. Touch Screen Setup for Interrupt Detection In addition to the measurements made above, the touch screen can also act as an interrupt source. In this mode the X plate of the touch screen has to be powered and the Y plate has to be grounded. In this case the touch screen is not biased by the active touch screen bias circuit, but by a resistor to vdda1. This configuration simply biases the touch screen and the UCB1100 does not consume power unless the touch screen is touched. The voltage on the X plate terminals drops if the screen is pressed. This voltage drop is detected by Schmitt trigger circuits, of which the outputs are connected to the interrupt control block. An touch screen interrupt is generated either when the touch screen is pressed (falling edge enabled) or when the touch screen is released (rising edge enabled). which can by used to activate the system around the UCB1100 to start a touch screen readout sequence. The internal Schmitt trigger circuits are connected to the tspx and tsmx signals after the built in low pass filters. This reduces the number of spurious interrupts, due to the coupling between the LCD screen and the touch screen sensors. Each of the four touch screen signals can be selected as input for the built in 10 bit ADC, which is used to determine the voltage on the selected touch screen pin. The flexible switch matrix and the multi functional touch screen bias circuit enables the user of the UCB1100 to set each desired touch screen configuration. The setting of the touch screen bias circuitry and the adc_input multiplexer is determined by the setting of the tsc_mod_sel bits in the touch screen control register according the following table.
adc_input_sel
analog mux
tsc_bias_ena
mux
tsc_mod_sel
to adc input
SN00142
Figure 17. Block Diagram of the Touch Screen Interface The touch screen interface connects to the touch screen by four wires: tspx, tsmx, tspy and tsmy. Each of these pins can be programmed to tbe floating, powered or grounded in the touch screen switch matrix. The setting of each touch screen pin is programmable by the power ts.. and ground ts.. bits in the touch screen control register. Possible conflicting settings (grounding and powering of a touch screen pin at the same time) are detected by the UCB1100. In that case the UCB1100 will ground the touch screen pin. The UCB1100's internal voltage reference (Vref) is as reference voltage for the touch screen bias circuitry. This makes the touch screen biasing independent of supply voltage and temperature variations. Four low pass filters, one on each touch screen terminal, are built in to minimize the noise coupled from the LCD into the touch screen signals. An LCD typically generates large noise glitches on the touch screen, since they are closely coupled.
1998 May 08
17
IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII
Xplate tsmx tspy comparator
tspx
SN00143
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
TOUCH SCREEN MODE SELECTION
tsc_mod_sel bits 00 01 10 11 selected mode interrupt pressure position position touch screen bias source resistor to vdda1 touch screen bias circuit touch screen bias circuit touch screen bias circuit `selected' adc input defined by adc_input_sel bits touch screen current monitor defined by adc_inp_sel bits defined by adc_input_sel bits
SUMMARY OF TOUCH SCREEN MODES
Touch screen measurement X position Y position pressure - 1 pressure - 2 pressure - 3 pressure - 4 pressure - 5 X plate resistance Y plate resistance interrupt tspx powered 1 adc input
2
tsmx grounded 1 adc input
2
tspy adc input 2 powered
1
tsmy adc input 2 grounded
1
touch screen mode position position pressure pressure pressure pressure pressure pressure
1
touch screen bias enabled enabled enabled enabled enabled enabled enabled enabled enabled disabled 3
powered 1 powered floating floating grounded powered 1 floating powered
powered 1 floating grounded powered floating grounded 1 floating powered
grounded 1 grounded powered floating floating floating powered
1
grounded 1 floating floating grounded powered floating grounded grounded
pressure interrupt
grounded
NOTES: 1. The powered and grounded touch screen pins may be interchanged. 2. One of the two indicated touch screen pins have to be selected. 3. The touch screen bias has to be disabled in this mode by the user, to prevent false interrupts.
6.4.1 Touch Screen Specifications
LIMITS SYMBOL VTSCBIAS ITSCMAX RTSCINT RSWGND tTSCSTR PARAMETER touch screen bias voltage maximum touch screen current maximum touch screen resistance to generate an interrupt on resistance ground switch start up time touch screen bias voltage generator CONDITIONS touch screen position mode selected touch screen position mode selected touch screen interrupt mode selected touch screen pin programmed grounded 10 2500 50 25 MIN TYP 1.8 MAX UNIT V mA s
1998 May 08
18
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.5 10 bit ADC
The UCB1100 includes a 10 bit successive approximation analogue to digital converter (ADC) with build in track and hold circuitry, an analogue multiplexer to select 4 analogue inputs or the 5 touch screen voltages and 4 switched resistive voltage dividers on the analogue ad0-3 high voltage inputs. The ADC is used to readout the touch screen inputs and it measures the voltage on the four analogue high voltage inputs ad0-3. The ADC is controlled through the SIB interface. It is enabled by the adc_enable bit in register 10; the ADC circuitry, including the track and hold circuitry does not consume any power when it is not enabled. A complete analogue to digital conversion consists of several phases. First the ADC input selector must be set to the proper input. Secondly the track and hold must track the signal; this requires a certain settling time if the adc input was changed. After this time the sample is taken. A calibration of the ADC circuitry is performed before the actual conversion starts. The result of the conversion is stored in the register 11 of the SIB interface, after the completion of
the conversion. An interrupt may be generated whenever a conversion is completed, depending of the setting of the adc_interrupt_ena bits in the sib register 2 and 3. The adc_data_valid bit in the SIB register 11 indicates the status of the ADC; it equals `0' when a ADC sequence is started and it equals `1' when the ADC result is stored in the SIB register 11. The ADC sequence is started in two ways. First it starts whenever the adc_start bit in register 10 is changed from `0' to `1'; this is the case when the adc_sync_ena bit in registers 10 equals `0' (=default). Internal logic determines whether the adc input multiplexer setting was changed in the sib frame, carrying the adc_start bit transition. If this is the case, an additional tracking time is added automatically. The second mode of operation is activated when the adc_sync_ena bit is set to `1'. In this mode the ADC conversion is not started by an `0' to `1' transition of the adc_start bis, but is `armed'. During the arming situation the track and hold circuit tracks the selected input signal. A sample is taken and the actual ADC conversion is started when a rising edge is detected on the adcsync input pin.
internal reference to external register 11 mux 10 bit ADC 9 to 1 track & hold 10 stop logic ADC start
adcsync
adc start sync enable
adc_sync_ena
SN00144
Figure 19. Block Diagram of the 10 bit ADC Circuit
tadcena adc_ena adc_input_selection tadctrk adc_start tadccal tconv 'adc state' adc_dat_valid adc_data track cal conversion track
SN00145
Figure 20. Timing Diagram of an ADC Conversion Sequence (adc_sync_ena=`0')
1998 May 08
19
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
The ADC sequence is started in two ways. First it starts whenever the adc_start bit in register 10 is changed from `0' to `1'; this is the case when the adc_sync_ena bit in registers 10 equals `0' (=default). Internal logic determines whether the adc input multiplexer setting was changed in the sib frame, carrying the adc_start bit transition. If this is the case, an additional tracking time is added automatically. The second mode of operation is activated when the adc_sync_ena bit is set to `1'. In this mode the ADC conversion is not started by an `0' to `1' transition of the adc_start bis, but is `armed'. During the arming situation the track and hold circuit tracks the selected input signal. A sample is taken and the actual ADC conversion is started when a rising edge is detected on the adcsync input pin. The internal ADC start logic adds a fixed tracking time, when the ADC input multiplexer was changed in the SIB frame with the `0' to `1' transition of the adc_start bit. A rising edge on the adcsync pin will not have any effect during this tracking time; the ADC sequence
will start on the first detected rising edge on the adcsyn pin after this tracking time. This mode is particulary useful when the internal ADC has to be synchronized with the external systems. Typically it is used to synchronize the readout of the touch screen with the driving of the LCD screen, which is normally placed in the direct neighborhood of the touch screen. Many spikes and a lot of `noise' are superposed on the touch screen signals, due to the close coupling of the touch screen and the LCD. The UCB1100 contains four high voltage analogue inputs ad0-3 which can be selected by the ADC input multiplexer, besides the already discussed touch screen interface signals. These high voltage inputs optimized to handle voltages larger than the applied supply voltage. The built in resistive voltage divider are only activated if the corresponding analogue input is selected. The not selected ad0-3 inputs are high ohmic resulting in minimal leakage input leakage of these pins.
tadcena adc_ena tadctrk adc_input_selection tadcdead adc_start tadcstrs adcsync tadccal tconv 'adc state' adc_dat_valid adc_data track cal conversion
SN00146
Figure 21. Timing Diagram of an ADC Conversion Sequence (adc_sync_ena=`1')
ad0 or ad1 or ad2 or ad3
adc input switch
adc_inp_sel[2:0]
SN00147
Figure 22. ad0-ad3 Resistive dividers
1998 May 08
20
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.5.1 Specification Overview
LIMITS SYMBOL RESADC VFSad RINad ILad DNLADC INLADC tconv tadccal tadctrk PARAMETER resolution of ADC full scale ad0-3 inputs input impedance selected ad0-3 pin input leakage current, non selected ad0-3 pins differential non-linearity integral non linearity conversion time settling time tracking time no adc input change adc input change tracking time no adc input change adc input change adc_sync_ena=`0' 1 50 adc_sync_ena=`1' 25 50 10 ns tsibclk ns tsibclk tsibclk 7.17 50 CONDITIONS MIN TYP 10 7.5 75 <1 0.1 0.5 110 10 7.9 100 10 0.5 2 MAX UNIT bit V A lsb lsb tsibclk tsibclk
tadctrks thadcsync tpadcsync
6.6 On Chip Reference Circuit
The UCB1100 contains an on chip reference voltage source, which generates the reference voltages for the 10 bit ADC and the necessary internal reference voltages. Alternatively, the UCB1100 can be driven from an external reference voltage source. The internal reference voltage can be monitored and filtered additionally on the vrefbyp pin. Two bits in the ADC control register determine the mode of operation of this reference voltage circuit. The vrefbyp_con bit connects the internal reference voltage to the vrefbyp pin, while the ext_vref_ena bit disables the internal reference voltage and switches the UCB1100 into the external voltage reference mode. The internal reference circuit is activated only when one or more analogue functions inside the UCB1100 is activated. This reduces the current consumption of the analogue part in standby mode. The external reference voltage source is also disconnected when all analogue functions are disabled.
aud_in_ena ext_vref_ena aud_out_ena tel_in_ena tel_out_ena tsc_bias_ena Internal & adc_ena internal reference voltage & circuitry vrefbyp_con vrefbyp
reference
SN00148
Figure 23. Block Diagram of the Reference Circuit
6.6.1 Specification Overview
LIMITS SYMBOL VREF trefstrt PARAMETER reference voltage start up time of internal reference voltage circuit CONDITIONS MIN 1.1 TYP 1.2 MAX 1.3 50 UNIT V tsibclk
1998 May 08
21
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.7 Serial Interface Bus
The UCB1100 serial interface bus (SIB) is compatible with industry standard serial ports and devices, and is designed to connect directly to a system controller. The sib protocol allows one or more slave devices to be connected to the system controller. The data transfer is always synchronous and it is frame based. The SIB interface consists of four signals: sibddn, sibdout, sibclk and sibsync. Each SIB frame consists of at least 64 clock cycles. Typically 128 bits are used, divided into 2 sub frames of 64 bits each. The first word (the bits 0 to 63) is read and/or written by the UCB1100, the remaining bits may be used for communication between the system controller and another slave device. The sibdout pin of the UCB1100 is default-stated for the bit 64 and higher in the SIB frame to prevent bus conflicts with other slave devices. However when the sib_zero_ena bit (control register 1) is set, the sibdout pin is forced to zero for bit 64 and higher to prevent floating of the sibdout line during this part of the sib frame in case when the UCB1100 is the only slave device connected to the bus. The UCB1100 always samples incoming data on the sibdin pin on the falling edge of sibclk and it outputs data on the sibdout pin on the rising edge of the sibclk. The start of a new sib frame is indicated by a pulse on the sibsync line just before the start of this new sib frame. The applied clock signal to the sibclk pin is used as clock signal inside the UCB1100; all internal clock signals are derived from that. It is required that the sibclk signal is applied if one or more analogue or digital functions is activated in the UCB1100; only the interrupt controller is implemented synchronously. The sibclk may be stopped when all digital and analogue functions are disabled; in that case the lowest possible power consumption is meet. The sibclk should not be stopped during a sib frame, but only at the end of the sib-frame, to ensure that all analogue and digital functions are stopped properly. NOTE: The interrupt controller is still active, due to its asynchronous implementation. The UCB1100 can therefore still generate interrupts to the system controller, when the sibclk is stopped.
The generation of the audio and telecom sample clocks require that the sibclk signal is symmetrical: a non symmetrical sibclk will lead to non equidistant sample moments, when an odd frequency divisor is set in either of the audio or telecom control registers.
SIB MASTER
UCB11001 sibclk sibsync sibdin sibdout
sibclk sibsync sibdout sibdin
SIB SLAVE 2 sibclk sibsync sibdin sibdout
TO OTHER SIB SLAVES
SN00149
Figure 24. Typical Connection Between the UCB1100 and the System Controller
bit 0 bit 1 sibclk
bit 2 bit 3
bit 62 bit 63
bit 64 bit 65 bit 126
bit 127 bit 0
sibsync
sibdin
sibdout #1
sibdout #2
SN00150
Figure 25. Serial Data Transmission of the UCB1100, sibdout #1 in case sib_zero bit = `0', sibdout #2 in case sib_zero bit = `1'
1998 May 08
22
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.7.1 SIB Data Format
The first 64 bits in the sib-frame are read and written by the UCB1100 and they contain both audio and telecom codec data fields, several control bits and a control register data field as is defined in table below. SIBDin field definition audio input path data [15:0]; bit 0 = MSB, the 12 MSB bits are read. not read but reserved control register address [3:0]; bit 0 = MSB SIBDout field definition audio output path data [15:0]; bit 0 = MSB, the bits [15:12] are `0' fixed `0' control register address [3:0]; bit 0 = MSB; = copy of the register address as present in the sibdin field in the same sib frame fixed zero fixed zeros audio valid flag telecom valid flag telecom output path data [15:0], bit 0 = MSB, the bits [15:14] are `0'' control register read data [15:0]; bit 0 = MSB
Sib frame bit 15-0
16 20-17
21 29-22 30 31 47-32
write bit (write = 1) not read but reserved audio valid sample flag telecom valid sample flag telecom input path data [15:0]; bit 0 = MSB, the 14 MSB bits are read. control register `write data [15:0]; bit 0 = MSB
63-48
NOTE: Since the data transfer is completely synchronous, a given control register may be written many times, before the device feeding the data has a chance to change the control bits. The UCB1100 does detect whether the data is changed or not.
1998 May 08
23
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.7.2 Codec Data Transfer
The audio and telecom codecs both operate at a programmable sample rate slower than the data transfer rate of the serial bus. The codecs sample the contents of the appropriate field each time their internal counters indicate that a new sample is necessary. They update the data read by the serial interface in the same manner. The counters for the audio and telecom subsystems are reset each time the respective subsection is turned on (whenever the audio/telecom input or output path enable bits are set) and counting begins at the next SIBSync input pulse (see Figure 26). The controlling devices must be both frequency and phase synchronized to the sample rate counters within the UCB1100 in order to ensure correct operation.
sibclk/128
sibdin
#1
codec enable
tcodstr sample counter 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3
sample pulse
SN00151
Figure 26. Start of the codec sample counters (divisor set to 7). Sibdin sub frame #1 contains the codec input and/or output path enable bit, the codec enable signal is the `OR' function of the associated code input and output enable bit. The codec data is loaded in the codec input register after the sub frame has been sent completely, when the appropriate data valid flag was set in the sib frame. The codec input data is not refreshed, whenever the audio and/or telecom data valid flag equals `0' in the sub frame or when no sibdin data is transmitted.
sibclk/128
sibdin stream
#1
#1
#1
#2
#2
#1
#1
#3
#3
#1
codec input data
N
N+1
N+2
N+3
N+4
N+5
SN00152
Figure 27. Codec input data handshake protocol, sibdin frame #1 contains codec data and the data valid flag equals `1', sib frame #2 contains codec data, but the data valid flag equals `0', sib frame #3 contains no data. Codec data must be received by the UCB1100 in one of the SIB frames preceding the sample moment of the codec, it uses the last sample received before the sample moment. In case no refreshed codec data has been sent, the UCB1100 re-uses the available `old' codec data sample. This will lead to high distortion in the codec circuits.
1998 May 08
24
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
sibclk/128
sample counter
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
sample pulse
sibdin
A,#1
B,#1
B,#2
C,#1
D,#1
D,#1
D,#1
D,#1
E,#1
E,#2
codec data
sample B
sample C
sample D
sample D
sample E
SN00153
Figure 28. Codec input data transfer, sib frame x,#1 contains sample x data with the associate data valid flag set to `1', the sib frame indicated with x,#2 contain the codec sample x, with the associated data valid flag set to `0'. The codec output data is transmitted in the first SIB frame following the sample moment of the codec. The sibdout data stream contains a data valid bit for each codec (bit 30 and bit 31) to simplify the data transfer from the UCB1100 to the system controller. The audio and telecom data valid bits are set to `1' in the sibdout data stream when the codec generate reliable data. This is the case when the codec circuitry is stabilized after it was enabled. This mode of operation is chosen when the dyn_vflag_ena bit (register 13) equals `0'. A second mode is available to simplify the transfer of data, which is set when the dyn_vflag_ena bit is set to `1'. In that case the audio and the telecom data valid flag bits will be `1' in the sib frame following the codec sample moment, which contains at all times the most recent codec result.
sibclk/128
sample counter
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
sample pulse
audio data
N
N
N+1
N+2
N+2
N+3
N+3
N+4
N+4
N+5
telecom data
N
N+1
N+2
N+2
N+3
N+3
N+4
N+4
N+5
N+6
data valid flag
SN00154
Figure 29. Sample counter synchronization (divisor set to 7), audio and telecom data placement shown in sibdout data stream, including the associated audio/telecom data valid flags (dynamic data valid flag mode). The audio and telecom codec data each are positioned as if they had 16 bits of resolution. For the 12-bit audio codec the low 4 bits are ignored on input and forced to 0 on output. For the 14-bit telecom codec, the low 2 bits are treated similarly.
1998 May 08
25
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.7.3 Control Register Data Transfer
The last 16 bits of the UCB1100 word is made up of control register data. The selection of the control register and whether it is read or written is defined by the control register address field [bit 17:20] and the "write" bit [bit 21]. For a read action on the a control register, the control register address field has to set to the desired control register address and the "write" bit has to be set to zero in the SIBDin stream, The read data is sent by the UCB1100 within the control register data field of SIBDout during the same frame as the read request occurred. In addition, during a read cycle, the control register data field of SIBDin is ignored by the UCB1100 which implies that no modifications of the UCB1100 settings can be performed when the "write" bit equals zero in the SIBDin data-stream. For a write cycle ("write" bit = 1), the control register data contents of SIBDin are written to the UCB1100 register selected by the register address field after receipt of the complete first word (the update is performed during the 64th bit in the SIB frame). This implies that the
control register data contents of SIBDout data-stream in a SIB frame represents the previous contents of the selected control register. The control register address in the sibdout data-stream is a copy of the selected control register in the sibdin data-stream. These bits show an additional delay since they pass additional circuitry in the UCB1100. The control register data is actually written in the control registers after the transfer of the first sib word is completed. This implies that the control register data is updated during bit 64 of the sib frame. The control data is only updated when the write bit is `1' in the sib frame. The control data will not be updated when the write bit equals `0'. This simplifies the read out of control register data, since it is not required to send `valid' data in the control register data field when a control register is read, if the write bit is kept at `0'. The control register data in the sibdout stream is sampled just before the sib frame is started. This implies that the returned control register data represents the `old' control data, in case new data was provided in the sibdin data stream.
tpcdu bit 63 sibclk bit 64 bit 65 bit 66
sibsync
sibdin
control data
SN00155
Figure 30. Control Register Update Timing
tsibclk tsclsy sibclk thclsy
tpcldo tscldi thcldi
sibsync tpdido sibdin
sibdout
SN00156
Figure 31. Timing Definitions SIB Interface
1998 May 08
26
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.7.4 AC Electrical Characteristics
Tamb = 0C to 70C, VSSD = VSSA1 = VSSA2 = VSSA3 = 0V VDDD = 3.3V 10%, VDDA1 = 3.3V 10%, VDDA2 = 3.3V 10% LIMITS SYMBOL 1/tsibclk thsibclk/tsibclk tsclsy thclsy tscldi thcldi tpcldo thcldo tpdido tpcdu NOTES: 1. This is a requirement when an odd divisor is set either in the audio or in the telecom codec. 2. This is valid for all sib frame bits 0 to 63, except bits 17-20. 3. This is valid for the sib frame bits 17-20. PARAMETER sibclk input frequency duty cycle sibclk sibsync valid to falling edge sibclk sibsync hold after falling edge sibclk sibdin valid to falling edge sibclk sibdin hold after falling edge sibclk rising edge sibclk to valid sibdout sibdout hold after rising sibclk edge valid sibdin to valid sibdout Note 2 Note 3 25 20 Note 1 NOTES MIN 0 50 TYP MAX 15 UNIT MHz % ns ns ns ns ns ns ns
6.8 General Purpose IOs
The UCB1100 has 10 programmable digital input/output (IO) pins. These pins can be independently programmed as input or output using the IO_mode[0:9] bits in the control register 1. The output data is determined by the content of the io_data bits in the control register 0, while the actual status of these pins can be read from the io_data[0:9] bits in the control register 0. The data on the io[0:9] pins are feed into the interrupt control block, where they can generate an interrupt on the rising and/or falling edge of these signals.
6.9 Interrupt Generation
The UCB1100 contains a programmable interrupt control block, which can generate an interrupt for a `0' to `1' and/or a `1' to `0' transition on one or more of the IO[0:9] pins, the audio and telecom clip detect, the adc_ready signal and the tspx_low and tsmx_low signals. The interrupt generation mode is set by the int_ris_ena bits in register 2 and the int_fal_ena bits in the control register 3. The actual interrupt status of each signal can be read from the control register 4. The interrupt status is clear whenever a `1' to `0' transition is written in control register 4 for the corresponding bit. The irqout pin presents the `OR' function of all interrupt status bits and can be used to give an interrupt to the system controller. The interrupt controller is implemented asynchronously. This provide the possibly to generate interrupts when the sibclk is stopped, e.g., an interrupt can be generated in power down mode, when the touch screen is pressed or when the state of one of the io pins changes.
io_dir[x]
io_dat_in[x]
io[x]
io_dat_out[x] `1' D
ris_int_ena[x]
`OR' tree
to interrupt module
SN00157
int. source
R & irqout
Figure 32. Block Diagram of I/O Pin Circuitry
& D
R fal_int_ena[x] int_stat[x] register 4 (read) int_clear[x] reset
SN00158
Figure 33. Block Diagram of the Interrupt Controller
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
6.10 Reset Circuitry
The nreset signal is captured in the UCB1100 using a asynchronous pulse stretching circuit. The nreset signal may be pulled down when the sibclk is still stopped. The internal circuitry remembers this reset signal and generates an internal reset signal from at least 5 sibclk periods.
COUNT 3 internal reset
arstn
& '1' D Q D Q D Q
R NRESET sibclk
SN00159
Figure 34. Block Diagram of the Reset Circuitry
sibclk
tlnrst trsti nreset
arstn
count
0
1
2
3
internal reset
SN00160
Figure 35. Timing Diagram of the Reset Circuitry LIMITS SYMBOL tlnrst trsti tpclrsti nreset pulse width width of internal reset signal delay between rising edge sibclk and internal reset PARAMETER CONDITIONS MIN 5 5 * tsibclk 25 TYP MAX UNIT ns ns ns
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Preliminary specification
Advanced modem/audio analog front-end
UCB1100
7.0 MISCELLANEOUS 7.1 Power Routing Strategy
The UCB1100 has nine power supply pins, since the UCB1100 contains five power supply regions within the circuit. The analogue and digital parts have their separate power supplies to reduce the interference between these parts. The speaker driver circuit is powered separately (vdda2/vssa2) from the other analogue circuit parts and the touch screen switch matrix has its own ground pin (vssa3). This separation in the analogue part reduces the interference between the speaker driver and the touch screen switch matrix, which has relatively large and fluctuating current consumption and the remaining parts of the analog. The vssd pins and the vssa1 pin are connected within the UCB1100 circuit. It is recommended to connect the vssd pins and the vssa1 directly to a ground plane on the PCB. The split in power supply connections should be maintained on the PCB to get optimal separation. Figure 36 shows the recommended PCB power supply strategy.
vddd
vddd
vdda1
UCB1100
vdda2 3.3V supply vssa2
vssa1
vssd
vssd
vssa3
SN00161
Figure 36. Recommended Power Supply Connection Strategy
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
8.0 CONTROL REGISTER OVERVIEW Address 0: IO port data register
BIT 9:0 MODE R/W SYMBOL io_data[9:0] REMARK The bits in the write register provide the data of the io pin when programmed as output. The bits in the read register return the actual state of the associated io pin. RESET 0
Address 1: IO port direction register
BIT 9:0 15 MODE R/W R/W SYMBOL io_dir[9:0] sib_zero REMARK If `1', the associated io pin is defined as output. If `0', the associated io pin is defined as input If `1', the sibdout pin is forced `0' during the second sib word. If `0', the sibdout pin tristated during the second sib word 0 RESET 0
Address 2: Rising edge interrupt enable register
BIT 9:0 11 12 13 14 15 MODE R/W R/W R/W R/W R/W R/W SYMBOL io_ris_int[9:0] adc_ris_int tspx_ris_int tsmx_ris_int tclip_ris_int aclip_ris_int REMARK If `1', the rising edge interrupt of the associated io pin is enabled If `1', the rising edge interrupt of the adc_ready signal is enabled If `1', the rising edge interrupt of the tspx signal is enabled If `1', the rising edge interrupt of the tsmx signal is enabled If `1', the rising edge interrupt of the telecom clip is enabled If `1', the rising edge interrupt of the audio clip is enabled RESET 0 0 0 0 0 0
Address 3: Falling edge interrupt enable register
BIT 9:0 11 12 13 14 15 MODE R/W R/W R/W R/W R/W R/W SYMBOL io_fal_int[9:0] adc_fal_int tspx_fal_int tsmx_fal_int tclip_fal_int aclip_fal_int REMARK If `1', the falling edge interrupt of the associated io pin is enabled If `1', the falling edge interrupt of the adc_ready signal is enabled If `1', the falling edge interrupt of the tspx signal is enabled If `1', the falling edge interrupt of the tsmx signal is enabled If `1', the falling edge interrupt of the telecom clip is enabled If `1', the falling edge interrupt of the audio clip is enabled RESET 0 0 0 0 0 0
Address 4: Interrupt clear/status register
BIT 9:0 MODE W R 11 W R 12 W R 13 W R 14 W R 15 W R SYMBOL io_int_clr[0:9] io_int_stat[9:0] adc_int_clr adc_int_stat tspx_int_clr tspx_int_stat tsmx_int_clr tsmx_int_stat tclip_int_clr tclip_int_stat aclip_int_clr aclip_int_stat REMARK A `0' to `1' transition clears the interrupt of the associate io pin Returns the actual interrupt status of the associated io pin A `0' to `1' transition clears the interrupt adc_ready signal Returns the actual interrupt status of the adc_ready signal A `0' to `1' transition clears the interrupt of the tspx signal Returns the actual interrupt status of the tspx signal A `0' to `1' transition clears the interrupt of the tsmx signal Returns the actual interrupt status of the tsmx signal A `0' to `1' transition clears the interrupt of the telecom clip Returns the actual interrupt status of the telecom clip A `0' to `1' transition clears the interrupt of the audio clip Returns the actual interrupt status of the audio clip 0 0 0 0 0 RESET 0
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Preliminary specification
Advanced modem/audio analog front-end
UCB1100
Address 5: Telecom control register A
BIT 6:0 7 MODE R/W R/W SYMBOL tel_div[6:0] tel_loop_ena REMARK Telecom codec sample rate divisor. Valid values are between [0010000] (=16) and [1111111] (=127) If `1', the loopback mode of within the telecom codec is enabled. RESET 16 0
Address 6: Telecom control register B
BIT 3 4 MODE R/W R W 6 11 13 14 15 R/W R/W R/W R/W R/W SYMBOL high_pass_ena] tel_clip tel_clip tel_att side_sup_ena tel_mute tel_in_ena tel_out_ena REMARK If `1', the voice band filter in the telecom input path is enabled The bit returns the actual telecom clip detection status. A `0' to `1' transition bit clears the telecom clip detection status If `1', the telecom input attenuation (6dB) is enabled. If `1', the sidetone suppression circuit is activated If `1', the telecom output is muted If `1', the telecom input path is activated If `1', the telecom output path is activated 0 0 0 0 0 0 RESET 0
Address 7: Audio control register A
BIT 6:0 11:7 MODE R/W R/W SYMBOL aud_div[6:0] aud_gain[4:0] REMARK Audio codec sample rate divisor. Valid values lie between [00000110] (=6) and [1111111] (=127). Audio input gain setting. Values range from [00000] (no gain) to [11111] (46.5dB gain) RESET 6 0
Address 8: Audio control register B
BIT 4:0 6 8 13 14 15 MODE R/W R/W R/W R/W R/W R/W SYMBOL aud_att[4:0] aud_clip_ena aud_loop aud_mute aud_in_ena aud_out_ena REMARK Audio output attenuation setting. Values range from [00000] (no attenuation) to [11111] (69dB attenuation). If `1', the audio clip detection circuitry is activated If `1', the loopback mode in the audio codec is activated. If `1', the audio output is muted If `1', the audio codec input path is activated. If `1', the audio codec output path is activated. RESET 0 0 0 0 0 0
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Preliminary specification
Advanced modem/audio analog front-end
UCB1100
Address 9: Touch screen control register
BIT 0 1 2 3 4 5 6 7 [9:8] MODE R/W R/W R/W R/W R/W R/W R/W R/W R/W SYMBOL tspx_pow tsmx_pow tspy_pow tsmy_pow tspx_gnd tsmx_gnd tspy_gnd tsmy_gnd tsc_mode[1:0] If `1', the tspx pin is powered If `1', the tsmx pin is powered If `1', the tspy pin is powered If `1', the tspy pin is powered If `1', the tspx pin is grounded If `1', the tsmx pin is grounded If `1', the tspy pin is grounded If `1', the tspy pin is grounded Touch screen operation mode 00 : interrupt mode 01 : pressure measurement mode 1x : position measurement mode If `1', the touch screen bias circuitry is activated. This bit returns the inverted state of the tspx pin, `0' is high voltage (pen up), `1' is low voltage (pen down) This bit returns the inverted state of the tsmx pin, `0' is high voltage (pen up), `1' is low voltage (pen down) REMARK RESET 0 0 0 0 0 0 0 0 0
11 12 13
R/W R/W R/W
tsc_bias_ena tspx_state tsmx_state
0
Address 10: ADC control register
BIT 0 1 4:2 MODE R/W R/W R/W SYMBOL adc_sync_ena vrefbyp_con adc_input[2:0] If `1', the adc sync mode is activated If `1', the internal reference voltage is connected to the vrefbyp pin. ADC input selection bits: 000: tspx 001: tsmx 010: tspy 011: tsmy 100 ad0 101: ad1 110: ad2 111: ad3 If `1', an external reference voltage has to be applied to the vrefbyp pin A `0' to `1' transition starts the adc conversion sequence. If `1', the adc circuit is activated REMARK RESET 0 0 0
5 7 15
R/W R/W R/W
ext_ref_ena adc_start adc_ena
0 0 0
Address 11: ADC data register
BIT 14:5 15 MODE R R SYMBOL adc_data[9:0] adc_dat_val Returns the ADC result Returns `0' if an adc conversion is in progress. Returns `1' if the 0 adc conversion is completed and the adc data is stored in the adc_data[9:0] register. REMARK RESET 0 0
Address 12: ID register
BIT 5:0 11:6 15:12 MODE R R R SYMBOL version[5:0] device[5:0] supplier[3:0] REMARK Returns 000011 for all the UCB1100 circuits meeting this specification. Returns 000000 for all the UCB1100 circuits meeting this specification. Returns 0001 for all the UCB1100 circuits meeting this specification. RESET
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
Address 13: Mode register
BIT 0 1 5-2 12 13 14 15 MODE R/W R/W R/W R/W R/W R/W R/W SYMBOL aud_test tel_test prod_test_mode dyn_vflag_ena aud_off_can REMARK If `1', the analogue audio test mode is activated If `1', the analogue telecom test mode is activated These bits select the build in production test modes (Note 1) (Note 1) (Note 1) RESET 0 0 0 0 0
If `1', the dynamic data valid flag mode is activated for both the audio and the telecom data valid flag. If `1', the offset cancelling circuit in the audio input path is disabled. Reserved bit for special function Reserved bit for special function
NOTES: 1. These bits can only be written if the test pin is `1'. 2. The functionality of the UCB1100 is changed when one or more test modes are activated.
Address 14: Reserved
BIT MODE SYMBOL REMARK This register is reserved for future use. RESET
Address 15: Null register
BIT 15:0 MODE R SYMBOL REMARK Returns [1111111111111111] at all times RESET
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
9.0 PACKAGE OUTLINES 9.1 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
NOTES
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Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1100
10.0 DEFINITIONS
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 05-98 Document order number: 9397 750 03868
Philips Semiconductors
1998 May 08 36

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